Search results Search for: Search Refine your results by duration: Any Under 5 mins Under 20 mins Over 20 mins Sort by: Relevance Views Date Compute Express Link™ (CXL): Exploring Coherent Memory and Innovative Use Cases Siamak Tavallaei,(Microsoft), Rob Blankenship,(Intel), and Kurt Lender, (Intel) CXL technology maintains a unified, coherent memory space between the CPU (host processor) and CXL devices allowing the device to expose its memory as... 2 years ago | 59 mins Compute Express Link: Proposed Enhancements to UEFI and ACPI Specifications Mahesh Natu (Intel) and Thanu Rangarajan (Arm) Compute Express Link (CXL) is a new high-speed CPU-to-Device and CPU-to-Memory interconnect designed to accelerate next-generation data center perform... 2 years ago | 39 mins Breaking the PCIe Latency Barrier with CXL Stephane Hauradou, Product Marketing As the Compute Express Link™ (CXL™) interconnect protocol is gaining in popularity, mainly driven by the promise of higher performance and lower laten... 2 years ago | 48 mins Introduction to Compute Express Link™ (CXL) Glenn Ward (Microsoft), Debendra Das Sharma (Intel), Kurtis Bowman (Dell EMC) A highly informative webinar about the CXL Consortium™ and its groundbreaking technology. Join Glenn Ward, CXL Consortium’s MWG Co-Chair and Chief of... 2 years ago | 57 mins Breaking the PCIe Latency Barrier with CXL (Chinese version) Yu-Cheng Liao, ASIC Architect As the Compute Express Link™ (CXL™) interconnect protocol is gaining in popularity, mainly driven by the promise of higher performance and lower laten... 2 years ago | 36 mins Compute Express Link™ (CXL™): Memory Challenges and CXL Solutions Chris Petersen (Facebook) and Prakash Chauhan (Google) Compute Express Link™ (CXL™) is an industry supported cache-coherent interconnect for processors, memory expansion and accelerators. CXL supports dyna... 2 years ago | 61 mins Breaking the PCIe Latency Barrier with CXL Stephane Hauradou, Product Marketing As the Compute Express Link™ (CXL™) interconnect protocol is gaining in popularity, mainly driven by the promise of higher performance and lower laten... 2 years ago | 47 mins Building Smart Scalable Storage SoCs with Embedded PCIe Switching (Chinese) Michael Yu - ASIC Designer As storage systems embrace NVMe and all-flash, the need for scalability coupled with constantly evolving application requirements prompt SoC architect... 1 year ago | 37 mins Building Smart Scalable Storage SoCs with Embedded PCIe Switching Stephane Hauradou, Product Marketing As storage systems embrace NVMe and all-flash, the need for scalability coupled with constantly evolving application requirements prompt SoC architect... 2 years ago | 46 mins Building Smart Scalable Storage SoCs with Embedded PCIe Switching Stephane Hauradou, Product Marketing As storage systems embrace NVMe and all-flash, the need for scalability coupled with constantly evolving application requirements prompt SoC architect... 2 years ago | 45 mins
