How to get new chip designs to market faster and reduce costs

There is an opportunity for a surge in innovation in the semiconductor industry while significantly reducing time-to-market for new chips. As transistors keep shrinking and design complexity keeps growing, increased manufacturing complexity boosts risk and cost — making time-to-market even more critical. The key lies in faster and agile compute and storage infrastructure for electronic design automation (EDA) workloads, as well as new design technology and adoption of the right cloud services. This webcast will provide a holistic view of electronic design infrastructure and explore how the right infrastructure can help you to better leverage resources, reduce operational costs and accommodate additional workloads, all while improving performance. We will also explore innovations in tools like virtual platforms and digital twin technology. In this webcast you will learn: • How infrastructure can help to reduce costs while increasing performance, even as storage demands continue to rise • If adopting a cloud model is right for you, and how to design a hybrid cloud infrastructure for EDA workloads • Trends and innovations in design tools and technologies • Discuss a recent customer success story Speaker Bio: Balachandran Rajendran CTO, Dell EMC Electronic Design Automation Bala has been with Dell Technologies since April 2018 as part of Global CTO office at Unstructured Data Solutions focused on Semiconductor and EDA vertical. Before Dell EMC, Bala worked at various organizations like Siemens, Synopsys , Silicon Image, Inphi and Samsung Research America in various roles leading and managing CAD tools, design flows, design methodology, IP management, infrastructure and IT. Design complexities are growing exponentially and so are the design flows and infrastructure needs. Bala believes that to solve the challenges facing semiconductor industry, the Design, CAD and IT teams need to work as an integrated and cohesive unit.