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Retimers to the Rescue: PCI Express® Specifications Reach Their Full Potential

As PCI Express® (PCIe®) specifications continue to double the transfer rates of previous generations, the technology can address a variety of needs for data-demanding applications. However, along with the progression of PCIe specifications, challenges like signal integrity and channel insertion loss arise as well. Retimers are mixed signal analog/digital devices that are protocol-aware and have the ability to fully recover data, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. These devices are fully defined in the PCI Express base specification, including compliance testing, and are used to combat issues that PCI Express faces.

In this PCI-SIG® hosted webinar, Kurt Lender of Intel and Casey Morrison of Astera Labs will offer solutions to conquer signal integrity and channel insertion loss challenges, explain the diagnostic capabilities of retimer technology and more.

About the Presenters
Kurt Lender is an Ecosystem Enabling Manager for Intel Corporation and a Marketing Workgroup Chair at PCI-SIG
Casey Morrison is the head of Systems and Applications at Astera Labs and a PCI-SIG member
Recorded Oct 9 2019 60 mins
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Presented by
Kurt Lender, Intel and Casey Morrison, Astera Labs
Presentation preview: Retimers to the Rescue: PCI Express® Specifications Reach Their Full Potential

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  • 在系統實施中無縫轉移至PCIe® 5.0技術 Dec 10 2020 1:00 am UTC 60 mins
    Liang Liu, Astera Labs
    運算密集型工作負載(如人工智慧、機器學習)受到企業和雲端資料中心廣泛採用,需要透過高速、低延遲的互連架構如PCI Express®(PCIe®)連接高效能、專用節點。從PCIe 4.0升級至PCIe 5.0技術將頻寬從16GT/s增加一倍至32GT/s,但同時每單位距離的訊號衰減也更大,對訊號傳輸距離和系統拓撲挑戰造成影響。本次線上技術研討會將探討PCIe 4.0和PCIe 5.0規範之間的變化,包括訊號完整性和系統設計帶來的挑戰。在實際運算拓撲中,這些變化必須在PCB材料、連接器類型和訊號調節裝置之間找到適當的平衡。

    透過客觀分析,最終目標是為觀眾提供一種優化訊號和鏈路完整性效能的方法,為支援PCIe 5.0技術應用的系統板載設計提供最佳實踐方式,並測試系統級互通性。最後,為了提升鏈路正常運行時間,並最大程度發揮PCIe架構吞吐量和延遲的潛能,我們也將探討通道位元錯誤率(Lane BER)與鏈路穩定性之間的關係。

    计算密集型工作负载(例如人工智能和机器学习)受到企业和云数据中心广泛采用,需要通过高速、低延迟的互连架构如PCI Express®(PCIe®)连接高性能、专用的节点。从PCIe 4.0升级到PCIe 5.0技术使得带宽从16GT/s倍增至32GT/s,但同时信号的衰减也更大,从而对信号传输距离和系统拓扑挑战造成影响。本次技术网络研讨会探讨了PCIe 4.0和PCIe 5.0规范之间的变化,包括信号完整性和系统设计带来的挑战。在实际应用中,这些变化必须在PCB材料、连接器类型和信号调节器件之间找到适当的平衡。

    通过客观分析,最终目标是为与会者提供一种优化信号和链路完整性性能的方法,为支持PCIe 5.0技术应用的系统板设计提供最优方法,并测试系统级互操作性。最后,为了提高链路正常运行时间且最大程度的发挥PCIe架构吞吐量和延迟的潜力,我们也探索了信道误码率(Lane BER)与链路稳定性之间的关系。
  • Seamless Transition to PCIe® 5.0 Technology in System Implementations Dec 9 2020 4:00 pm UTC 60 mins
    Jonathan Bender, Casey Morrison and Pulkit Khandelwal, Astera Labs
    Compute-intensive workloads, such as Artificial Intelligence and Machine Learning, are being widely adopted in enterprise and cloud data centers, requiring high-performance, purpose-built nodes connected over high speed, low latency interconnects such as PCI Express® (PCIe®) architecture. The upgrade from PCIe 4.0 to PCIe 5.0 technology doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, impacting signal reach and system topology challenges. This technical webinar explores changes between PCIe 4.0 and PCIe 5.0 specifications, including signal integrity and system design challenges, where the right balance must be found between PCB materials, connector types and the use of signal conditioning devices for practical compute topologies.

    Through an objective analysis, the goal is to provide the audience with a methodology to optimize signal and link integrity performance, present best practices for system board design to support PCIe 5.0 technology applications, and test for system level interoperation. Finally, to improve link uptime and maximize the potential of PCIe architecture throughput and latency, we explore the relationship between Lane BER and Link stability.
  • Integrity and Data Encryption (IDE) ECN Deep Dive Recorded: Aug 25 2020 59 mins
    David Harriman, Protocol Work Group Chair, Intel
    Developers must focus on a wide number of considerations when securing the wide spectrum of systems, devices and components. Not only must they protect key assets against a litany of attacks, but they must also prioritize securing the entire component lifecycle. Over the past few years, PCI-SIG has focused on optimizing security features within the PCI Express library of specifications. This webinar will focus on the key aspects of the latest emerging security ECN: Integrity and Data Encryption (IDE).

    Attendees will learn about the next level details of motivations and use models, including Link vs. Selective, how security is managed, required elements outside of PCIe technology including software, system construction and industry infrastructure. The webinar will also provide an overview of Device’s responsibilities in maintaining security, such as how keys must be secured, paths around encryption eliminated/blocked and how to handle debug. Finally, the webinar will outline specific areas for feedback such as key size and key programming protocol.
  • PCIe® 6.0 Specification: The Interconnect for I/O Needs of the Future Recorded: Aug 5 2020 67 mins
    Debendra Das Sharma, PCI-SIG Board Member, Intel
    PCI Express® (PCIe®) architecture has provided the I/O connectivity for computing, communication, and storage platforms satisfying the power-efficient and low-latency requirements of cloud, enterprise, PC, embedded, IoT, automotive, and mobile market segments for two decades. However, the demand for additional performance in power constrained devices and data-hungry server, client, embedded, cloud and edge segments keeps increasing. To continue to meet the performance needs of these segments, PCI-SIG® continues its nearly three decade history of successfully delivering performance doubling with the development of the upcoming PCIe 6.0 specification.

    In this webinar, attendees will learn more about what is driving the quick transition to PCIe 6.0, including an updated specification release timeline. The webinar will feature a deep dive into the PCIe 6.0 architecture metrics. It will introduce the approach PCIe 6.0 specification is taking to offer new features like PAM-4 encoding and FEC, while preserving its low-latency characteristics required for a Load-Store interconnect and full backwards compatibility.
  • PCIe® 6.0 Specification: The Interconnect for I/O Needs of the Future Recorded: Jun 4 2020 60 mins
    Debendra Das Sharma, PCI-SIG Board Member, Intel
    PCI Express® (PCIe®) architecture has provided the I/O connectivity for computing, communication, and storage platforms satisfying the power-efficient and low-latency requirements of cloud, enterprise, PC, embedded, IoT, automotive, and mobile market segments for two decades. However, the demand for additional performance in power constrained devices and data-hungry server, client, embedded, cloud and edge segments keeps increasing. To continue to meet the performance needs of these segments, PCI-SIG® continues its nearly three decade history of successfully delivering performance doubling with the development of the upcoming PCIe 6.0 specification.

    In this webinar, attendees will learn more about what is driving the quick transition to PCIe 6.0, including an updated specification release timeline. The webinar will feature a deep dive into the PCIe 6.0 architecture metrics. It will introduce the approach PCIe 6.0 specification is taking to offer new features like PAM-4 encoding and FEC, while preserving its low-latency characteristics required for a Load-Store interconnect and full backwards compatibility.
  • Emerging Form Factors: EDSFF Overview Recorded: Apr 8 2020 60 mins
    Tom Friend (Illuminosi), Jonmichael Hands (Intel) and Jonathan Hinkle (Lenovo)
    Enterprise & Data Center SSD Form Factor (EDSFF) is one of the newest form factors to emerge in recent years. Its goal is to develop a stronger data center system-optimized design than traditional SSD form factors like M.2 or U.2. EDSFF has shown that it’s able to meet customer need for storage devices with its high density, capacity and performance.

    In this PCI-SIG® hosted webinar, our experts will provide an overview of the relationship between EDSFF and the PCI Express® (PCIe®) specifications and discuss various use cases for E1.L, E1.S and E3. Finally, they will outline the step-by-step process of how you can build a drive utilizing EDSFF form factors.
  • Retimers to the Rescue: PCI Express® Specifications Reach Their Full Potential Recorded: Oct 9 2019 60 mins
    Kurt Lender, Intel and Casey Morrison, Astera Labs
    As PCI Express® (PCIe®) specifications continue to double the transfer rates of previous generations, the technology can address a variety of needs for data-demanding applications. However, along with the progression of PCIe specifications, challenges like signal integrity and channel insertion loss arise as well. Retimers are mixed signal analog/digital devices that are protocol-aware and have the ability to fully recover data, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. These devices are fully defined in the PCI Express base specification, including compliance testing, and are used to combat issues that PCI Express faces.

    In this PCI-SIG® hosted webinar, Kurt Lender of Intel and Casey Morrison of Astera Labs will offer solutions to conquer signal integrity and channel insertion loss challenges, explain the diagnostic capabilities of retimer technology and more.

    About the Presenters
    Kurt Lender is an Ecosystem Enabling Manager for Intel Corporation and a Marketing Workgroup Chair at PCI-SIG
    Casey Morrison is the head of Systems and Applications at Astera Labs and a PCI-SIG member
One Interconnect, Infinite Applications
PCI-SIG is the organization that defines the PCI Express® (PCIe®) I/O bus specifications and related form factors.

Our channel will feature quarterly webinars covering topics like PCIe specification overviews, PCI-SIG compliance and interoperability, PCIe form factors, PCIe applications and more.

Our webinars will be presented by PCI-SIG technology experts from leading technology companies.

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  • Presented by: Kurt Lender, Intel and Casey Morrison, Astera Labs
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