PCIe® 6.0 Specification: The Interconnect for I/O Needs of the Future

Compute-intensive workloads, such as Artificial Intelligence and Machine Learning, are being widely adopted in enterprise and cloud data centers, requiring high-performance, purpose-built nodes connected over high speed, low latency interconnects such as PCI Express® (PCIe®) architecture. The upgrade from PCIe 4.0 to PCIe 5.0 technology doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, impacting signal reach and system topology challenges. This technical webinar explores changes between PCIe 4.0 and PCIe 5.0 specifications, including signal integrity and system design challenges, where the right balance must be found between PCB materials, connector types and the use of signal conditioning devices for practical compute topologies.

Through an objective analysis, the goal is to provide the audience with a methodology to optimize signal and link integrity performance, present best practices for system board design to support PCIe 5.0 technology applications, and test for system level interoperation. Finally, to improve link uptime and maximize the potential of PCIe architecture throughput and latency, we explore the relationship between Lane BER and Link stability.

Developers must focus on a wide number of considerations when securing the wide spectrum of systems, devices and components. Not only must they protect key assets against a litany of attacks, but they must also prioritize securing the entire component lifecycle. Over the past few years, PCI-SIG has focused on optimizing security features within the PCI Express library of specifications. This webinar will focus on the key aspects of the latest emerging security ECN: Integrity and Data Encryption (IDE).

Attendees will learn about the next level details of motivations and use models, including Link vs. Selective, how security is managed, required elements outside of PCIe technology including software, system construction and industry infrastructure. The webinar will also provide an overview of Device’s responsibilities in maintaining security, such as how keys must be secured, paths around encryption eliminated/blocked and how to handle debug. Finally, the webinar will outline specific areas for feedback such as key size and key programming protocol.

PCI Express® (PCIe®) architecture has provided the I/O connectivity for computing, communication, and storage platforms satisfying the power-efficient and low-latency requirements of cloud, enterprise, PC, embedded, IoT, automotive, and mobile market segments for two decades. However, the demand for additional performance in power constrained devices and data-hungry server, client, embedded, cloud and edge segments keeps increasing. To continue to meet the performance needs of these segments, PCI-SIG® continues its nearly three decade history of successfully delivering performance doubling with the development of the upcoming PCIe 6.0 specification.

In this webinar, attendees will learn more about what is driving the quick transition to PCIe 6.0, including an updated specification release timeline. The webinar will feature a deep dive into the PCIe 6.0 architecture metrics. It will introduce the approach PCIe 6.0 specification is taking to offer new features like PAM-4 encoding and FEC, while preserving its low-latency characteristics required for a Load-Store interconnect and full backwards compatibility.

PCI Express® (PCIe®) architecture has provided the I/O connectivity for computing, communication, and storage platforms satisfying the power-efficient and low-latency requirements of cloud, enterprise, PC, embedded, IoT, automotive, and mobile market segments for two decades. However, the demand for additional performance in power constrained devices and data-hungry server, client, embedded, cloud and edge segments keeps increasing. To continue to meet the performance needs of these segments, PCI-SIG® continues its nearly three decade history of successfully delivering performance doubling with the development of the upcoming PCIe 6.0 specification.

In this webinar, attendees will learn more about what is driving the quick transition to PCIe 6.0, including an updated specification release timeline. The webinar will feature a deep dive into the PCIe 6.0 architecture metrics. It will introduce the approach PCIe 6.0 specification is taking to offer new features like PAM-4 encoding and FEC, while preserving its low-latency characteristics required for a Load-Store interconnect and full backwards compatibility.

Enterprise & Data Center SSD Form Factor (EDSFF) is one of the newest form factors to emerge in recent years. Its goal is to develop a stronger data center system-optimized design than traditional SSD form factors like M.2 or U.2. EDSFF has shown that it’s able to meet customer need for storage devices with its high density, capacity and performance.

In this PCI-SIG® hosted webinar, our experts will provide an overview of the relationship between EDSFF and the PCI Express® (PCIe®) specifications and discuss various use cases for E1.L, E1.S and E3. Finally, they will outline the step-by-step process of how you can build a drive utilizing EDSFF form factors.

As PCI Express® (PCIe®) specifications continue to double the transfer rates of previous generations, the technology can address a variety of needs for data-demanding applications. However, along with the progression of PCIe specifications, challenges like signal integrity and channel insertion loss arise as well. Retimers are mixed signal analog/digital devices that are protocol-aware and have the ability to fully recover data, extract the embedded clock and retransmit a fresh copy of the data using a clean clock. These devices are fully defined in the PCI Express base specification, including compliance testing, and are used to combat issues that PCI Express faces.

In this PCI-SIG® hosted webinar, Kurt Lender of Intel and Casey Morrison of Astera Labs will offer solutions to conquer signal integrity and channel insertion loss challenges, explain the diagnostic capabilities of retimer technology and more.

About the Presenters
Kurt Lender is an Ecosystem Enabling Manager for Intel Corporation and a Marketing Workgroup Chair at PCI-SIG
Casey Morrison is the head of Systems and Applications at Astera Labs and a PCI-SIG member