Debendra Das Sharma, PCI-SIG Board Member, Intel
PCI Express® (PCIe®) architecture has provided the I/O connectivity for computing, communication, and storage platforms satisfying the power-efficient and low-latency requirements of cloud, enterprise, PC, embedded, IoT, automotive, and mobile market segments for two decades. However, the demand for additional performance in power constrained devices and data-hungry server, client, embedded, cloud and edge segments keeps increasing. To continue to meet the performance needs of these segments, PCI-SIG® continues its nearly three decade history of successfully delivering performance doubling with the development of the upcoming PCIe 6.0 specification.
In this webinar, attendees will learn more about what is driving the quick transition to PCIe 6.0, including an updated specification release timeline. The webinar will feature a deep dive into the PCIe 6.0 architecture metrics. It will introduce the approach PCIe 6.0 specification is taking to offer new features like PAM-4 encoding and FEC, while preserving its low-latency characteristics required for a Load-Store interconnect and full backwards compatibility.