Compute-intensive workloads, such as Artificial Intelligence and Machine Learning, are being widely adopted in enterprise and cloud data centers, requiring high-performance, purpose-built nodes connected over high speed, low latency interconnects such as PCI Express® (PCIe®) architecture. The upgrade from PCIe 4.0 to PCIe 5.0 technology doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, impacting signal reach and system topology challenges. This technical webinar explores changes between PCIe 4.0 and PCIe 5.0 specifications, including signal integrity and system design challenges, where the right balance must be found between PCB materials, connector types and the use of signal conditioning devices for practical compute topologies.
Through an objective analysis, the goal is to provide the audience with a methodology to optimize signal and link integrity performance, present best practices for system board design to support PCIe 5.0 technology applications, and test for system level interoperation. Finally, to improve link uptime and maximize the potential of PCIe architecture throughput and latency, we explore the relationship between Lane BER and Link stability.