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Compute Express Link™ (CXL): Exploring Coherent Memory and Innovative Use Cases

CXL technology maintains a unified, coherent memory space between the CPU (host processor) and CXL devices allowing the device to expose its memory as coherent in the platform and allowing the device to directly cache coherent memory. This allows both the CPU and device to share resources for higher performance and reduced software stack complexity. In CXL, the CPU host is primarily responsible for coherency management abstracting peer device caches and CPU caches. The resulting simplified coherence model reduces the device cost, complexity and overhead traditionally associated with coherency across an I/O link.

Please join Siamak Tavallaei, CXL Consortium Technical Task Force Co-Chair and Principal Architect, Microsoft Azure, Rob Blankenship, Processor Architect and Principal Engineer, Intel, and Kurt Lender, CXL Consortium Marketing Working Group Co-Chair and Senior Ecosystem Enabling Manager, Data Center Group, Intel, for a deep dive into how CXL technology maintains memory coherency between the CPU memory space and memory on attached devices. The webinar will also detail several representative CXL use cases – Caching Devices/Accelerators, Accelerators with Memory, and Memory Buffers.

Following the webinar, we will host an audience Q&A, so be sure to bring your questions.
Recorded Mar 12 2020 59 mins
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Presented by
Siamak Tavallaei,(Microsoft), Rob Blankenship,(Intel), and Kurt Lender, (Intel)
Presentation preview: Compute Express Link™ (CXL): Exploring Coherent Memory and Innovative Use Cases

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  • Compute Express Link™ (CXL™): Memory Challenges and CXL Solutions Recorded: Aug 6 2020 61 mins
    Chris Petersen (Facebook) and Prakash Chauhan (Google)
    Compute Express Link™ (CXL™) is an industry supported cache-coherent interconnect for processors, memory expansion and accelerators. CXL supports dynamic multiplexing between a rich set of protocols that includes I/O (CXL.io, based on PCIe®), caching (CXL.cache) and memory (CXL.memory) semantics. CXL.mem allows a host processor to access memory attached to a CXL device. CXL.mem transactions are simple memory load and store transactions that run downstream from the host processor which takes care of all the associated coherency flows.

    This webinar will explore how the CXL.mem protocol can deliver power-efficient performance with emerging applications such as AI, HPC, DL and comms with a coherent interface and low latency. This webinar will also explore type-3 devices and use cases for memory bandwidth expansion, memory capacity expansion and storage class memory.
  • Compute Express Link™ (CXL): Exploring Coherent Memory and Innovative Use Cases Recorded: Mar 12 2020 59 mins
    Siamak Tavallaei,(Microsoft), Rob Blankenship,(Intel), and Kurt Lender, (Intel)
    CXL technology maintains a unified, coherent memory space between the CPU (host processor) and CXL devices allowing the device to expose its memory as coherent in the platform and allowing the device to directly cache coherent memory. This allows both the CPU and device to share resources for higher performance and reduced software stack complexity. In CXL, the CPU host is primarily responsible for coherency management abstracting peer device caches and CPU caches. The resulting simplified coherence model reduces the device cost, complexity and overhead traditionally associated with coherency across an I/O link.

    Please join Siamak Tavallaei, CXL Consortium Technical Task Force Co-Chair and Principal Architect, Microsoft Azure, Rob Blankenship, Processor Architect and Principal Engineer, Intel, and Kurt Lender, CXL Consortium Marketing Working Group Co-Chair and Senior Ecosystem Enabling Manager, Data Center Group, Intel, for a deep dive into how CXL technology maintains memory coherency between the CPU memory space and memory on attached devices. The webinar will also detail several representative CXL use cases – Caching Devices/Accelerators, Accelerators with Memory, and Memory Buffers.

    Following the webinar, we will host an audience Q&A, so be sure to bring your questions.
  • Introduction to Compute Express Link™ (CXL) Recorded: Dec 12 2019 57 mins
    Glenn Ward (Microsoft), Debendra Das Sharma (Intel), Kurtis Bowman (Dell EMC)
    A highly informative webinar about the CXL Consortium™ and its groundbreaking technology.

    Join Glenn Ward, CXL Consortium’s MWG Co-Chair and Chief of Staff, Cloud Server Infrastructure for Microsoft; Debendra Das Sharma, Intel Fellow at Intel Corporation; and Kurtis Bowman, CXL Consortium Board Member and Director, Server Architecture and Technologies at Dell EMC during this thought-provoking webinar about the organization and its innovative technology. Topics covered include the industry landscape, features and benefits, use cases and more! All audience members are encouraged to bring questions for the Q&A portion of the webinar. Learn about how the organization operates and how to get involved.
CXL™ Consortium: Breakthrough CPU-to-Device Interconnect
Compute Express Link™ (CXL™) is a new breakthrough high-speed CPU interconnect that enables a high-speed, efficient performance between the CPU and platform enhancements and workload accelerators.



Industry leaders Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel Corporation and Microsoft have teamed up to form an open industry standard group to develop technical specifications that facilitate breakthrough performance for emerging usage models while supporting an open ecosystem for data center accelerators and other high-speed enhancements.

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  • Title: Compute Express Link™ (CXL): Exploring Coherent Memory and Innovative Use Cases
  • Live at: Mar 12 2020 3:00 pm
  • Presented by: Siamak Tavallaei,(Microsoft), Rob Blankenship,(Intel), and Kurt Lender, (Intel)
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