Presented by
Mahesh Wagh (Intel) and Rick Sodke (Microchip)
Compute Express Link™ 2.0 Specification: Memory Pooling
About this talk
Compute Express Link™ (CXL™) is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and devices such as accelerators, memory buffers, and smart I/O devices. In November 2020, the CXL Consortium announced the CXL 2.0 specification which introduces support for switching, memory pooling, and support for persistent memory – all while preserving industry investments by supporting full backward compatibility.
In this webinar, Mahesh Wagh (Intel) and Rick Sodke (Microchip), will explore how CXL 2.0 supports memory pooling for multiple logical devices (MLD) as well as a single logical device with the help of a CXL switch. This presentation will also introduce the standardized fabric manager for inventory and resource allocation to enable easier adoption and management of CXL-based switch and fabric solutions.
CXL® Consortium
6448 subscribers21 talks
CXL® Consortium: Breakthrough CPU-to-Device Interconnect
Compute Express Link® (CXL®) is a new breakthrough high-speed CPU interconnect that enables a high-speed, efficient performance between the CPU and platform enhancements and workload accelerators.
Industry leaders Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel Corporation and Microsoft have teamed up to form an open industry standard group to develop technical specifications that facilitate breakthrough performance for emerging usage models while supporting an open ecosystem for data center accelerators and other high-speed enhancements.