Introducing the CXL 3.1 Specification

Presented by

Mahesh Wagh, AMD, and Rob Blankenship, Intel

About this talk

The CXL 3.1 Specification introduces enhancements to fabric capability and manager API definition for PBR switch, inter-host communication using Global Integrated Memory (GIM), Trusted-Execution-Environment Security Protocol (TSP), and memory expander improvements. These enhancements will enable composable and disaggregated systems to keep up with the demand for high-performance computational workloads. This webinar will introduce the CXL 3.1 specification and explore the new features including: • CXL Fabric improvements and extensions • Trusted-Execution-Environment Security Protocol (TSP) • Memory expander improvements
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Compute Express Link® (CXL®) is a new breakthrough high-speed CPU interconnect that enables a high-speed, efficient performance between the CPU and platform enhancements and workload accelerators. Industry leaders Alibaba, Cisco, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei, Intel Corporation and Microsoft have teamed up to form an open industry standard group to develop technical specifications that facilitate breakthrough performance for emerging usage models while supporting an open ecosystem for data center accelerators and other high-speed enhancements.