ASIL-D compliant memory in the design of next-gen ADAS systems

We will explore options for building a safety case for systematic faults and random faults, in respect to the addition of DRAM and non-volatile memory to Micron’s safety roadmap. We will then describe our failure modes, effects and diagnostic analysis (FMEDA) approach for random fault mitigation, explain how DRAM can fail and which top-level failure modes (TLFM) are visible from host side. We will outline the issues with standard JEDEC DRAM and how Micron’s safety mechanisms help reach the hardware KPIs required for each ASIL level. Lastly, we will discuss the importance of system-level availability and traditional trade-offs associated with safety. What you’ll learn: o The fundamentals of safety, including: ISO26262 standard, systematic vs. random fault coverage, top-level safety requirements, concepts of classification and detection o The arguments for automotive-qualified safety-compliant memories and storage o About Micron’s automotive-qualified ASIL compliant safety solutions portfolio and associated features