Breaking the PCIe Latency Barrier with CXL

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Presented by

Stephane Hauradou, Product Marketing

About this talk

As the Compute Express Link™ (CXL™) interconnect protocol is gaining in popularity, mainly driven by the promise of higher performance and lower latency for CPU to Device communication, many questions arise around expected latency improvement. In this presentation, we describe the data flow model for the 3 protocols that comprise CXL (CXL.io, CXL.cache, CXL.mem) in contrast to traditional PCI Express, and look at the implications in terms of latency at the system level. We then present a couple of specific use cases that would clearly benefit a lower latency CXL interconnect and conclude with a look at the PLDA Controller IP for CXL and the design features allowing optimal CXL performance in silicon chips.

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Rambus makes industry-leading chips and IP that advance data center connectivity and solve the bottleneck between memory and processing. The ongoing shift to the cloud, along with the widespread advancement of AI across data center, 5G, automotive and IoT, has led to an exponential growth in data usage and tremendous demands on data infrastructure. Creating fast and safe connections, both in and across systems, remains one of the most mission-critical design challenges limiting performance in advanced hardware. Rambus is ideally positioned to address this challenge as an industry pioneer with over 30 years of advanced semiconductor interconnect experience moving and protecting data. We are a leader in high-performance memory subsystems, providing chips, IP and innovations that maximize the performance and security in data-intensive systems. Whether in the cloud, at the edge or in your hand, real-time and immersive applications depend on data transfer speed and trust. Rambus products and innovations deliver the increased bandwidth, capacity and security required to usher in a new era of data center architectures and drive ever-greater end-user experiences.