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Building Smart Scalable Storage SoCs with Embedded PCIe Switching

As storage systems embrace NVMe and all-flash, the need for scalability coupled with constantly evolving application requirements prompt SoC architects to look for ways to differentiate and future-proof their designs.

In this presentation we look at current storage architectures and propose an innovative way to design next-generation storage SoCs centered around the use of embedded PCIe switching.

We then introduce PLDA’s PCIe switch IP along with some real-world use cases, and explore the various IP features and capabilities that enable differentiation and future-proofing of SoCs in storage applications and beyond.
Live online Sep 29 3:00 pm UTC
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Presented by
Stephane Hauradou, Product Marketing
Presentation preview: Building Smart Scalable Storage SoCs with Embedded PCIe Switching

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  • Building Smart Scalable Storage SoCs with Embedded PCIe Switching Sep 29 2020 3:00 pm UTC 60 mins
    Stephane Hauradou, Product Marketing
    As storage systems embrace NVMe and all-flash, the need for scalability coupled with constantly evolving application requirements prompt SoC architects to look for ways to differentiate and future-proof their designs.

    In this presentation we look at current storage architectures and propose an innovative way to design next-generation storage SoCs centered around the use of embedded PCIe switching.

    We then introduce PLDA’s PCIe switch IP along with some real-world use cases, and explore the various IP features and capabilities that enable differentiation and future-proofing of SoCs in storage applications and beyond.
  • Breaking the PCIe Latency Barrier with CXL Recorded: Sep 1 2020 47 mins
    Stephane Hauradou, Product Marketing
    As the Compute Express Link™ (CXL™) interconnect protocol is gaining in popularity, mainly driven by the promise of higher performance and lower latency for CPU to Device communication, many questions arise around expected latency improvement. In this presentation, we describe the data flow model for the 3 protocols that comprise CXL (CXL.io, CXL.cache, CXL.mem) in contrast to traditional PCI Express, and look at the implications in terms of latency at the system level. We then present a couple of specific use cases that would clearly benefit a lower latency CXL interconnect and conclude with a look at the PLDA Controller IP for CXL and the design features allowing optimal CXL performance in silicon chips.
  • Breaking the PCIe Latency Barrier with CXL Recorded: Jul 16 2020 48 mins
    Stephane Hauradou, Product Marketing
    As the Compute Express Link™ (CXL™) interconnect protocol is gaining in popularity, mainly driven by the promise of higher performance and lower latency for CPU to Device communication, many questions arise around expected latency improvement. In this presentation, we describe the data flow model for the 3 protocols that comprise CXL (CXL.io, CXL.cache, CXL.mem) in contrast to traditional PCI Express, and look at the implications in terms of latency at the system level. We then present a couple of specific use cases that would clearly benefit a lower latency CXL interconnect and conclude with a look at the PLDA Controller IP for CXL and the design features allowing optimal CXL performance in silicon chips.
  • Breaking the PCIe Latency Barrier with CXL (Chinese version) Recorded: Jul 16 2020 36 mins
    Yu-Cheng Liao, ASIC Architect
    As the Compute Express Link™ (CXL™) interconnect protocol is gaining in popularity, mainly driven by the promise of higher performance and lower latency for CPU to Device communication, many questions arise around expected latency improvement. In this presentation, we describe the data flow model for the 3 protocols that comprise CXL (CXL.io, CXL.cache, CXL.mem) in contrast to traditional PCI Express, and look at the implications in terms of latency at the system level. We then present a couple of specific use cases that would clearly benefit a lower latency CXL interconnect and conclude with a look at the PLDA Controller IP for CXL and the design features allowing optimal CXL performance in silicon chips.
PLDA: Experts in High Speed Interconnect
PLDA is a developer and licensor of Semiconductor Intellectual Property (SIP) specializing in high-speed interconnect supporting multi-gigabit rates (2.5G, 5G, 8G, 16G, 25G, 32G, 56G, 112G), and protocols such as PCI Express, CCIX, CXL, and Gen-Z. PLDA has established itself as a leader in that space with over 3,200 customers and 6,400 licenses in 62 countries. PLDA is a global technology company with offices in Silicon Valley, France, Bulgaria, Taiwan, and China.

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  • Title: Building Smart Scalable Storage SoCs with Embedded PCIe Switching
  • Live at: Sep 29 2020 3:00 pm
  • Presented by: Stephane Hauradou, Product Marketing
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