In a few short years, CXL (Compute Express Link) has evolved from an idea to a rapidly proliferating low latency interconnect standard being adopted into data centers, high performance computing, and cloud computing. However, as the adoption has increased, so has the security threat model users face. To address this, the CXL 2.0 standard has included an optional IDE (Integrity and Data Encryption). While IDE is optional today, given ever-increasing security threats, it won’t be forever so understanding IDE will become essential.
 
In this webinar, Rambus and Siemens will discuss the background of IDE, the threat models it addresses, and how zero latency IDE’s can provide assurances to CXL adopters. Design and verification engineers and managers won’t want to miss this webinar to understand how to incorporate and validate this essential standard in their designs.

CXL and IDE: Important Considerations of Protecting High Speed Interconnects

The latest generation of the PCI Express, PCIe 5.0, advances performance to 32 GT/s in support of advanced applications including 400G Ethernet. In this webinar, Rambus technology experts Malini Narayanamoorthi and Vinitha Seevaratnam discuss the selection and implementation considerations for PCI Express solutions. A demonstration of the silicon-proven Rambus PCIe 5.0 interface solution consisting of integrated PHY and memory controller will be shown.

Selection and Implementation of a PCIe 5.0 Subsystem

As the need for data has exploded driven by applications like AI/ML and automotive, the semiconductor industry, led by PCI-SIG, is preparing for the final release of the PCIe 6.0 specification and all the changes it entails.

In this first of two joint webinars, PLDA and Siemens EDA join to introduce you to PCIe 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.

What you will learn:

- what is PCIE 6.0
- how does it differ from past generations
- design considerations when planning with PCIe 6
- verification implications of a PCIe 6 design

Preparing for PCIe 6.0

Over the course of two decades, PCI Express® (PCIe®) has become the de-facto I/O interconnect in electronic systems, by providing the level of performance and reliability expected by cloud, enterprise, consumer, industrial, and automotive applications.
However the explosion of data in recent years has accelerated the need for higher performance interconnects, prompting PCI SIG® to quickly transition to PCIe 6.0 with the imminent release of the PCIe 6.0 specification.
In this webinar, we present the main characteristics of the PCIe 6.0 protocol in contrast to earlier revisions, and explain the rationale behind the main architecture changes. We then take a look at PCIe 6.0 from the perspective of silicon IP enablement, by introducing the main design features required to take full advantage of the new level of performance offered by PCIe 6.0.

Get ready for PCIe® 6.0, the next generation of I/O interconnect

As storage systems embrace NVMe and all-flash, the need for scalability coupled with constantly evolving application requirements prompt SoC architects to look for ways to differentiate and future-proof their designs.

In this presentation we look at current storage architectures and propose an innovative way to design next-generation storage SoCs centered around the use of embedded PCIe switching.

We then introduce PLDA’s PCIe switch IP along with some real-world use cases, and explore the various IP features and capabilities that enable differentiation and future-proofing of SoCs in storage applications and beyond.

Building Smart Scalable Storage SoCs with Embedded PCIe Switching (Chinese)

Exponential data growth is driving the need for increased performance in Enterprise and Data Center applications, and resulted in the emergence of new interconnect technologies such as CXL and CCIX, and faster transition to PCIe 5.0 and PCIe 6.0. This presentation looks at the different protocol technologies and introduces PLDA and Alphawave joint Controller and PHY IP solution for the Samsung Advanced Process Nodes.  
We describe the joint solution in terms of features and capabilities, and present the stringent verification and validation methodology in place to guarantee first-pass silicon success for Samsung Foundry customers.

Enabling next-generation SoC on Samsung Foundry with PCIe 5.0/6

Building Smart Scalable Storage SoCs with Embedded PCIe Switching

As the Compute Express Link™ (CXL™) interconnect protocol is gaining in popularity, mainly driven by the promise of higher performance and lower latency for CPU to Device communication, many questions arise around expected latency improvement. In this presentation, we describe the data flow model for the 3 protocols that comprise CXL (CXL.io, CXL.cache, CXL.mem) in contrast to traditional PCI Express, and look at the implications in terms of latency at the system level. We then present a couple of specific use cases that would clearly benefit a lower latency CXL interconnect and conclude with a look at the PLDA Controller IP for CXL and the design features allowing optimal CXL performance in silicon chips.

Building Smart Scalable Storage SoCs with Embedded PCIe Switching

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