Name: A Novel Packet-Based Accelerator for Resource-Constrained Edge Devices
Start: 2022-06-14T17:00:00Z
End: 2022-06-14T17:00:32.000Z
Location: BrightTALK
Rating: 0

Expedera provides scalable neural engine semiconductor IP that enables major improvements in performance, power, and latency while reducing cost and complexity in AI inference applications. Third-party silicon validated, Expedera’s solutions produce superior performance and are scalable to a wide range of applications from edge nodes and smartphones to automotive and data centers. Expedera’s Origin deep learning accelerator products are easily integrated, readily scalable, and can be customized to application requirements. The company is headquartered in Santa Clara, California. Visit expedera.com

Always-sensing cameras are emerging in smartphones, home appliances, and other consumer devices, much like the always-listening Siri or Google voice assistants. Always-on technologies enable a more natural and seamless user experience, allowing such features as automatic locking and unlocking of the device or display adjustment based on the user's gaze. However, camera data has quality, richness, and privacy concerns which requires specialized Artificial Intelligence (AI) processing. However, existing system processors are ill-suited for always-sensing applications.  Without careful attention to Neural Processing Unit (NPU) design, an always-sensing sub-system will consume excessive power, suffer from excessive latency, or risk the privacy of the user, all leading to an unsatisfactory user experience. To process always-sensing data in a power, latency, and privacy-friendly manner, OEMs are turning to specialized “LittleNPU” AI processors. In this webinar, we’ll explore the architecture of always-sensing, discuss use cases, and provide tips for how OEMs, chipmakers, and system architects can successfully evaluate, specify, and deploy an NPU in an always-on camera sub-system.

An Ideal Neural Processing Engine for  Always-sensing Deployments

A relatively new class of processor, the NPU (Neural Processing Unit), is taking its place in heterogeneous designs. As a result, chip designers who rarely consider creating custom CPU or GPU architectures are grappling with whether to design their own custom NPUs. This talk will highlight the complexities of designing NPUs and explore why a better option might be a silicon-proven, packet-based AI engine that allows you to customize for current and future workloads.

Cautions of Designing Your Own NPU

艾伯德的统一计算流水线架构 IP 支持高效的硬件调度和高级内存管理，从而实现优秀的端到端低延迟性能。该架构已在数学上被证明，为神经网络 (NN) 执行使用的内存最少。我们的 Origin™ 深度学习加速器 IP 使系统设计人员能够满足一系列低延迟、节能和高性能要求。这将大幅降低芯片面积，减少 DRAM 访问，提高带宽，节省功耗，并显著提高性能。由于神经网络会生成大量中间数据，因此，通过尽量减少内存，可以在片上实时运行高分辨率神经网络处理，如 4K/8K 视频。艾伯德 Origin 以理想的 IP 大小提供卓越性能，易于集成和扩展，并可根据您的独特需求进行定制。对于功率受限的应用，如耳机和智能扬声器，我们提供 TimbreAI T3，这是一款超低功率 AI 推理引擎，专为音频降噪而设计。

最优神经网络加速 基于数据包架构

This video is a brief introduction to the Expedera TimbreAI T3: a Artificial Intelligence (AI) accelerator IP designed to run audio de-noising algorithms within the smallest power and area constraints.

TimbreAI: An Ideal AI Accelerator for Audio De-noising Applications

In specifying the features, functions, and requirements of a main processor and AI accelerator (NPU), system engineers and chip architects often don't consider use cases. In this webinar, Expedera VP of Marketing Paul Karazuba and Andes Technology Director of Field Applications John Min will examine typical use cases system designers face, and the considerations that should be factored when deciding on main processor and AI accelerator performance requirements.

Important Considerations for Specifying a Main Processor and AI Accelerator

As AI capability is beginning large-scale deployment into edge devices, many wonder about the decision to use a specialized AI accelerator, rather than simply using the systems main processor. In this first of two webinars on the topic, Paul Karazuba, VP of Marketing at Expedera, and John Min, Director of Field Application Engineering at Andes Technology, will explore the state of the art of CPUs and AI processing, and examine why leading semiconductor companies are adopting hybrid core architecture that combines a main processor with a specialized AI processor.

Optimized Chip Design with Main Processors and AI Accelerators

In this short webinar, VP of Business Development Nancy Gomes provides a brief introduction to Expedera, including our company history and the Expedera Origin Deep Learning Accelerator (DLA) Artificial Intelligence Inference IP.

Introduction to Expedera

This webinar provides a high level overview of Expedera's unique Packet-based architecture for AI Acceleration, including a background on traditional AI acceleration work units, how our packet-based architecture functions, and real-world implementation data showing breakthrough AI Inference performance, power, and area implementations.

Optimal Neural Network Acceleration via a Packet-based Architecture by Expedera

AI is rapidly moving from cloud platforms into edge devices, with edge processors rapidly incorporating hardware accelerators for real-time AI processing. Faced with tight cost, bandwidth and power consumption constraints, edge AI processors must still deliver the high performance required by system developers. In this talk, Expedera co-founder and Chief Scientist Sharad Chole will discuss the problems chip designers and system architects face in trying to apply AI within tight power, performance, and area budgets, and how state-of-the-art packet-based NPUs (Neural Processing Units) can be employed to meet and beat system design goals.

A Novel Packet-Based Accelerator for Resource-Constrained Edge Devices

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A Novel Packet-Based Accelerator for Resource-Constrained Edge Devices

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