SmartNICs to xPUs – Why is the Use of Accelerators Accelerating?

Presented by

Joseph White, Dell; Jai Menon, Fungible; Lior Khermosh, NeuReality; John Kim, NVIDIA; Alex McDonald, Independent Consultant

About this talk

As applications continue to increase in complexity and users demand more from their workloads, there is a trend to again deploy dedicated accelerator chips to assist or offload the main CPU. These new accelerators (xPUs) have multiple names such as SmartNIC, DPU, IPU, APU, NAPU. How are these different than GPU, TPU, CPU? xPUs accelerate and offload functions including math, networking, storage, cryptography, security, and management. This webcast will cover key topics about, and clarify questions surrounding, xPUs, including… 1. xPU Definition: What is an xPU (SmartNIC, DPU, IPU, APU, NAPU), GPU, TPU, CPU? A focus on high-level architecture and definition of the xPU. 2. Trends and Workloads: What is driving the trend to use hardware accelerators again after years of software-defined everything? What types of workloads are typically offloaded or accelerated? 3. Deployment and Solutions: What are the pros and cons of dedicated accelerator chips versus running everything on the CPU? 4. Market landscape Who provides these new accelerators—the CPU, storage, networking, and/or cloud vendors? How do cost and power factor in? On May 19th, join us for Part 1 of this xPU Series to get the answers to these questions. Part 2 of this series will take a deep dive on accelerator offload functions and Part 3 will focus on deployment and solutions.
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