Software Defined Packet Processing in FPGAs with P4

Presented by

Awanish Verma, Sr. Manager and Architect “SDN/NFV”, Xilinx Inc.

About this talk

Programmability with flexibility in the network has gained traction in the market due to a variety of use cases. Customers are looking to differentiate the infrastructure with programmability and the addition/removal of custom packet headers.  The emerging custom protocols and flexible packet processing in edge, access and data center networks has created the demand for defining the packet processing in high level languages.  This requirement is further stressed with SDN and NFV based networks requiring modification of the packet processing logic without knowledge of underlying hardware. To this end, the newly emerging language P4 is widely being viewed as the de-facto standard in standards based packet processing.   Xilinx is co-chairing the P4 Language Design group, and has developed a compiler to compile programs written in P4 into Xilinx FPGA binary images. This compiler has been demonstrated at the P4 Workshop series held at Stanford University in 2015-16, and at the major SIGCOMM conference this year.    Xilinx All programmable FPGAs offer a unique architectural advantages for these requirements, since they offer programmable logic together with programmable interconnect to a large number of DSP units, SRAM blocks, hardened IO interfaces, and 100GE Ethernet MACs and PCIe blocks.  These attributes make it the suitable architecture for the packet processing for today and the future generation of programmable networks.

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